The present invention claims priority from Japanese Patent Application No. 11-298209 filed Oct. 20, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) switch to be used in a digital communication network, and more particularly to an output buffer type ATM switch having a buffer for each circuit at the output side.
2. Description of Related Art
Up to now, an output buffer type ATM switch out of ATM switches used in a digital communication network is provided with switch ports having the same transmission rate as one another and being equal in number at the input side and the output side, respectively.
FIG. 9 shows a composition example of a conventional output buffer type ATM switch, and shows an output buffer type ATM switch having a switch capacity of 5 G bps which is provided with eight switch ports each having a transmission rate of 600 Mbps at each of the input and output sides.
As shown in FIG. 9, this composition example, which switches cells transmitted between eight input circuits 130-1 to 130-8 and eight output circuits 140-1 to 140-8, comprises input ports 121-1 to 121-8 which have each a transmission rate of 600 Mbps and have cells inputted from the input circuits 130-1 to 130-8, input buffers 122-1 to 122-8 for temporarily storing in them cells inputted through the input ports 121-1 to 121-8, a multiplexer 111 for multiplexing and outputting cells inputted through the input ports 121-1 to 121-8 onto a bus having a transmission rate of 5 G bps, address filters 112-1 to 112-8 which are respectively provided correspondingly to the output circuits 140-1 to 140-8 and each of which makes only the cells addressed to its own circuit out of cells multiplexed by the multiplexer 111 pass through it, output buffers 113-1 to 113-8 for temporarily storing in them the cells which have passed through the address filters 112-1 to 112-8, and output ports 114-1 to 114-8 which have each a transmission rate of 600 Mbps and output the cells outputted from the output buffers 113-1 to 113-8 to the output circuits 140-1 to 140-8. Although not illustrated, a logical connection number/output circuit number conversion table for identifying a logical connection number from a VP (virtual path)/VC (virtual channel) written in the header of an inputted cell and giving an output circuit number being an output destination corresponding to a cell having the logical connection number is provided at a stage before the said ATM switch.
A switching operation of an output buffer type ATM switch composed as described above is described in the following.
When cells from the input circuits 130-1 to 130-8 are inputted through 121-1 to 121-8, the inputted cells are multiplexed by the multiplexer 111, and are outputted onto a bus having a transmission rate of 5 G bps. Next, only the cells addressed to their own output circuits by their circuit numbers out of the cells which have been multiplexed by the multiplexer 111 and outputted onto the bus pass respectively through the address filters 112-1 to 112-8 provided respectively correspondingly to the output circuits 140-1 to 140-8, and are inputted into the output buffers 113-1 to 113-8. In the output buffers 113-1 to 113-8, the cells outputted onto the bus at a transmission rate of 5 G bps from the multiplexer 111 are temporarily stored and are outputted at a transmission rate of 600 Mbps. After that, the cells outputted from the output buffers 113-1 to 113-8 are outputted through the output ports 114-1 to 114-8 to the output circuits 140-1 to 140-8.
Hereupon, in order to prevent cells from being discarded in case that overflow of the cells occurs due to a fact that outputting the cells lags behind inputting the cells in the output buffers 113-1 to 113-8, a control of sending a back pressure signal to the input buffers 122-1 to 122-8 is performed. A threshold value is provided to each of the output buffers 113-1 to 113-8, and when the number of cells staying in an output buffer exceeds this threshold value, the relevant output buffer sends a back pressure signal to all the input buffers 122-1 to 122-8. The input buffers 122-1 to 122-8 temporarily stop sending cells addressed to an output circuit corresponding to the output buffer sending a back pressure signal out of the output circuits 140-1 to 140-8. By this, cells are prevented from being discarded in the output buffers 113-1 to 113-8 in which there is the possibility that overflow of cells occurs.
In a digital communication after now, with the increase of traffic capacity it is required to realize switching of cells in connection having a capacity not less than the transmission rate of a switch port in an ATM switch. For example, it is required to enable an ATM switch which is provided with a plurality of switch ports each having a transmission rate of 600 Mbps and has a switch capacity of 5 G bps like the above-mentioned output buffer type ATM switch to contain a circuit having a transmission rate of 2.4 G bps and set a connection having a band of 600 Mbps or more.
Since an output buffer type ATM switch as described above has ports being equal in transmission rate to one another, however, it cannot switch a connection having a band being higher than the transmission rate of an input port. For example, cells inputted from an input port at a transmission rate of 600 Mbps can be outputted to an output port at a transmission rate of 600 Mbps, but cells from an input circuit having a transmission rate of 2.4 G bps and a connection band of 800 Mbps cannot be inputted into this input port.
In order to meet such a requirement, it is conceivable to improve the capability of a device forming an ATM switch and form a switch having the same architecture and switch ports made higher in transmission rate, but in this case there is a problem that a switch having switch ports made higher in transmission rate must be newly designed and an excessive time and cost are required for designing such a switch.
The present invention has been performed in consideration of the problems of the prior art as described above, and aims at providing an output buffer type ATM switch capable of switching cells of a connection higher in transmission rate than an existing switch port by means of an existing switch.
In order to attain the above-mentioned object, the present invention provides an output buffer type ATM switch comprising;
a plurality of input ports into which cells from input circuits are inputted,
a first multiplexer for multiplexing cells inputted through said plurality of input ports,
a plurality of output ports for sending out cells to output circuits,
a plurality of filters which are provided correspondingly to said output ports and make only the cells addressed to the corresponding output ports out of cells multiplexed by said first multiplexer pass through them, and
a plurality of output buffers for temporarily storing in them the cells which have passed through said plurality of filters, in which ATM switch the cells stored in said plurality of output buffers are outputted to said output circuits through said plurality of output ports, wherein;
at least one input port out of said plurality of input ports and at least one output port out of said plurality of output ports are respectively a high-speed input port and a high-speed output port each having a transmission rate being 2 or larger integer times higher than the other input and output ports, respectively, and
said ATM switch comprises;
numbering parts which are provided correspondingly to said plurality of input ports and add a sequence number indicating the order in which said cell has been inputted for its logical connection number to a cell inputted from each of said plural input ports,
a demultiplexer for separating cells which are inputted through said high-speed input port and each are added a number by said numbering part to a plurality of paths so that said cells become equal in transmission rate to cells inputted through the other input ports than said high-speed input port,
a second multiplexer for multiplexing and outputting cells outputted from a plurality of output buffers corresponding to said high-speed output port out of said plurality of output buffers at the transmission rate of said high-speed output port, and
order restoring parts which are provided correspondingly to said plurality of output ports and which, on the basis of said sequence numbers added to the cells multiplexed and outputted by said second multiplexer and the cells outputted from the other output buffers than the output buffers corresponding to said high-speed output port, correct the order of outputting said cells and output them, and wherein;
said first multiplexer multiplexes the cells inputted through the other input ports than said high-speed input port and the cells separated by said demultiplexer.
And the present invention is characterized by an output buffer type ATM switch comprising input buffers in which cells inputted through said plurality of input ports are temporarily stored, wherein;
each of said plurality of output buffers sends a signal to stop the cells addressed to the output buffer itself being sent to said input buffers when the number of cells to be stored in the said output buffer exceeds a predetermined threshold value, and
each of said input buffers temporarily stores in it cells addressed to the output buffer which has sent said signal when it receives the said signal.
And the present invention is characterized by an output buffer type ATM switch wherein said input buffers are provided correspondingly to said plurality of input ports.
And the present invention is characterized by an output buffer type ATM switch wherein said numbering part comprises;
a header information detecting part for detecting an output circuit number and a logical connection number from a cell inputted through said input port,
a sequence number table in which a sequence number added to a cell transmitted at the last time by a logical connection is set for each logical connection number,
an output buffer number table in which information about said plurality of output buffers is stored,
a sequence number control part for retrieving said sequence number and said output buffer number from said sequence number table and said output buffer number table on the basis of an output circuit number and a logical connection number detected by said header information detecting part, and
a cell header information adding part for adding a sequence number and an output buffer number retrieved by said sequence number control part to a cell.
And the present invention is characterized by an output buffer type ATM switch wherein said order restoring part comprises;
a cell distributing part for distributing cells to each connection on the basis of logical connection numbers added to the cells,
a plurality of cell order restoring parts each of which corrects the order of sending cells on the basis of sequence numbers added to the cells, and
a cell multiplexing part for multiplexing cells corrected in order of sending by said plurality of cell order restoring parts.
And the present invention is characterized by an output buffer type ATM switch wherein said output buffer number table stores in it the number of each of said output circuits, the forefront output buffer number and the end output buffer number in an output circuit corresponding to each output circuit number, and the latest output buffer number added to a cell transmitted at the last time out of output buffers included between the forefront output buffer number and the end output buffer number.
And the present invention is characterized by an output buffer type ATM switch wherein said sequence number control part, when adding said output buffer number to a cell, increments said latest output buffer number, sets said incremented number as a number to be added to the cell in case that the incremented number is not larger than the end output buffer number in said output circuit, and sets said latest buffer number as a number to be added to the cell as the forefront output buffer number in the said output circuit in case that the incremented number is larger than the end output buffer number.
And the present invention is characterized by an output buffer type ATM switch wherein said sequence number control part, when adding said sequence number to a cell, increments a sequence number corresponding to a logical connection number added to the cell, sets said incremented number as a number to be added to the cell in case that the incremented number is not larger than a number capable of being processed by said order restoring part, and sets said sequence number at xe2x80x9c0xe2x80x9d in case that the incremented number is larger than the number capable of being processed by said order restoring part and then sets a number obtained by incrementing the said number as a number to be added to the cell.
And the present invention is characterized by an output buffer type ATM switch wherein said sequence number control part, when a signal to stop a cell addressed to said output buffer being sent is sent from the said output buffer, does not add a cell the number of the output buffer which has sent the said signal.
In the present invention composed as described above, at least one input port out of a plurality of input ports and at least one output port out of said plurality of output ports are respectively a high-speed input port and a high-speed output port each having a transmission rate being 2 or larger integer times higher than the other input and output ports, respectively, and cells from an input circuit being higher in transmission rate are inputted through said high-speed circuit and separated by a demultiplexer so as to become ordinary in transmission rate. After this, cells separated by the demultiplexer and cells inputted through other input ports are multiplexed by a multiplexer and cells addressed to the respective circuits pass through a plurality of filters, respectively and are temporarily stored in output buffers and are outputted at transmission rates of the corresponding output ports to the output circuits. Cells to be outputted through the high-speed output port are temporarily stored in output buffers and then are multiplexed by the second multiplexer, and thereby the cells are made to have the transmission rate of the high-speed output port and are outputted through the high-speed output port to the output circuit.
Hereupon, it is necessary to compensate the order of outputting cells inputted from input ports from output ports. Thereupon, a cell is added a sequence number by providing a number adding part for adding the order of an inputted cell to the cell correspondingly to its input port. After this, the order of sending out the cells outputted from the output buffers is rearranged by the order restoring part to the order of being inputted on the basis of numbers added to said cells and thereby the order of sending out the cells is compensated.